Memories with self refresh mode are becoming more and more common. For instance synchronous dynamic random access memories (SDRAMs) presenting these features are sold by Fujitsu, NEC, Samsung and other memory suppliers, and are used extensively in recent computers. U.S. Pat. No. 5,262,998 (Mnich et al.) discloses a DRAM exhibiting a sleep or low power mode of operation, entered in response to a single externally applied signal.
It is also a trend in the computer industry to provide sleep or low power modes for computers and associated monitors. This is based on environnemental considerations, and practical considerations, e.g. for laptop computers. Therefore, a standard for controlling the setting a processor into sleep mode has been defined as part of the recent Advanced Configuration and Power Interface (ACPI) specification.
In recent processors, it has been possible to set the processor in a sleep mode by applying a sleep signal to a specific pin of the processor, as for instance the STPCLK# of the Pentium.TM. Pro microprocessors sold by Intel Corp. The processor, when receiving the sleep signal carries out certain tasks for ensuring that it can correctly resume operation when woken up, these tasks including internal clean-up and update of memory. The processor may then transmit on the processor bus a transaction indicating that it is passing into sleep mode; in the case of the Pentium Pro processor, a STPCLK ACK transaction is sent on the bus when the processor passes into sleep mode.
However, there is no standardized solution at the system level for setting a memory to the sleep or low power mode. One solution is disclosed for instance in EP-A-0 632 463 (Casio Computer Company). This document discloses an electronic device with a CPU, a pseudo-SRAM having a sleep mode and a specific circuit for sending sleep signals to the CPU and to the pseudo-SRAM. This approach requires specific hardware solutions; furthermore, inasmuch as the memory sleep mode is not yet standardized, this approach may only be used for memories of a given type.
U.S. Pat. No. 5,262,998 suggests that the memory sleep mode may be entered in response to a command from the CPU, the memory controller being trigged by this command to generate a sleep signal for putting the memory chips into the sleep mode. This solution is disadvantageous in that the processor needs to run specific firmware for entering the sleep mode. This solution also means that the processor must know which type of command it should issue to set the memory into its sleep mode. Again, this limits the use of this solution to certain types of memories or memory controllers.
A similar problem is encountered at wake-up. The processor will not work properly if the memory is still in its sleep mode. The solution to this wake up problem according to EP-A-0 632 463 is to send the wake up signal to the memory before sending the wake up signal to the processor. This solution has the same drawback, i.e. implies using a specific circuit. U.S. Pat. No. 5,262,998 does not address this wake up problem where the memory sleep mode is entered in response to a command from the CPU: it rather provides a specific memory sleep mode which is transparent to the CPU and allows rapid resumption of active cycles.
There exists a need for a solution to control sleep mode in electronic devices, that is of a more general nature than the specific hardware and firmware solutions described above.